Target interface analysis

Website security:

I have updated this website to default to TLS for connections.  I have a certificate supplied by my hosting provider.  I have also turned on member accounts.  I am hoping this will make it more convenient you, the readers to join the conversation.

Voltage level shifter:

I am still trying to decide the best way to go for adjusting to the target platform voltage.  SPI typically needs 3 bits output (SS, SCLK, MOSI) and one bit input(MISO)  Sometimes SPI needs more. JTAG needs 4 pins output(TCK, TMS, TDO, TRST) and one bit input(TDI). I found the JTAG signal description on this page. I2C needs two bits of bi-directional open drain signals.  I don’t know of any MicroControllers that can be programmed over I2C but there are flash memories that are programmed that way.

Based on this information, I can see that I would want 4 bits of output and 2 input along with a 2 bit open drain bi-directional.  This gives me a total of eight bits of data available to connect to the target device.  In addition to that, I need Target Vcc and GND and Vpp. Continue reading

Schematic update

Arduino compass toy:

I have had a little time to play with the OLED panel this week. Unfortunately, I still can’t get it to work.  I have been trying to get it to work in SPI mode, But I think I now want to try to start working in either 8080 or 6800 modes.

Schematic Update:

I updated the schematic to reflect the results of my testing from 2 weeks ago.

I still need to try a high gain transistor in place of the one I used to see what will happen.

I am waiting to make some decisions before I update the schematic on GitHub.


Continue reading

Understanding HSPI Firmware V00H

What I wasn’t understanding last week is the definition of HSPI_CS.  It is the same as CS0 in the HSPI module.  So when I turn on overlap mode, of course, it maps to SPI_CS0.  That leaves me with setting the HSPI to use CS1(GPIO1/U0TXD) or CS2(GPIO0).  Since I use U0TXD for reprogramming the module, CS1 is unavailable.

I cut the trace going to U2 CS0 and added a jumper wire to GPIO0.  I then changed the code to use CS2 to enable the RAM.  This included setting the HSPI to use CS2 and setting GPIO0 MUX to be SPICS2.  And I got what looks like a successful write to the SPI RAM.

Successful SPI Write

The byte command (2) followed by 24bit address (0) followed by the data.  The first four bytes of data are “lleH”.  This is backwards to what I was planning, I can change it by setting a bit or changing the bytes I put into the registers. As long as I read them back the same way, it really doesn’t matter as long as I read and write aligned to 4 byte words.  The data is one byte short, I had a typo sending only 11 bytes of data.

Note: When data is aligned to 4 bytes, it means you need to read or write only on increments of 4 bytes.  So you would only Write or Read to/from addresses that in hexadecimal end in 0, 4, 8, or C. Since this chip is a 32 bit processor, this is required often.

I then decided to implement the hard coded read command.  I copied the write code, changed the command from 2 to to 3, set the HSPI to read back  and zeroed out the working registers so that I can see if they have been filled with the data I stored in the RAM. Then I commented out the writeRam() call in user_init and added readRam() in it’s place. Doing this without powering down, I should get the data back without having to write it again. I forgot to switch the length to the receive length register; I fixed this then I got back all zeros for the data.

Unsuccessful SPI read

I see the command (3) followed by the address (0) followed by 12 Bytes of data(0). So I have more debugging to do.  My first guess is the WP or HOLD lines of the chip are not doing what I need them to do.

I have gotten a better understanding of the SPI hardware on the ESP8266.  It looks to me that I can get the same control by just using the main SPI channel to control my RAM chip.  This needs testing.  I will need to save any registers I change and restore them when I am done accessing the RAM.  This will also have to be done from code that runs from internal RAM.

I have put the current state of the code on GitHub.  Use the link under the search box on the right side of this page.

Have you used chips with similar SPI configuration?  I like that I can have any bit length of data on the SPI bus, this will be useful for JTAG data. Have you worked directly with JTAG data?

Programming interface circuitry

The ESP-12E operates on a voltage between 3.0 and 3.5 Volts. The devices that I want this programmer to service could have operational voltages as low at 1.8 Volts and as high as 5 Volts.  Some routers operate on 12 Volts but their programming logic is probably in the 1.8 to 5.5 V range.

I searched for “level shifters” on the web and found a nice option from NXP.  The 74LVC2T45 is a dual supply, two bit Bi-directional buffer.  Maximum propagation delay is 10.1 nS  which would be compatible with JTAG speeds up to about 50 Mbps.  This would allow me to configure the I/O direction of each pair of bits at the connector.

Except for high voltage programming enable pins, These chips should be able to handle all the voltages for programming devices.  I will still have to design the programming enable voltage pins separately.

I am adding this new IC into the custom library and I will place several on the schematic.Interface Circuitry

Processor Option 3

The MSP432P401RIRGC is an ARM Cortex M4F processor.  It has a web based IDE (integrated development environment). It has six serial communication modules and runs up to 48 MHz. This chip started out looking good, however it doesn’t look very good after a little bit of research.  A quick look back at the Microchip processor (Processor Option 2) showed me that this processor is probably not a good fit for this design.  Unless I eliminate the other processor options, I will not use this chip.  The chip not being available yet plays a large part of this decision. If it becomes available before I start prototyping, I may change my mind.

Side Note:

For my abbreviations I will always use an upper case B to represent bytes and a lower case b to represent bits.  For instance 1,000 bytes will be represented as 1 KB and 1,000,000 bits will be represented at 1 Mb.



Device Advantages

  • SPI up to 16Mbps with DMA
  • 256 KB Flash code space
  • 64 KB RAM space (16 bit address pointers are very easy to work with in C)

Device Disadvantages

  • Not available yet
  • Large pin count (64 pin for smallest variant)
  • No DIP part for prototyping
  • US $5.59 in quantities of 1K (Kind of high) may come down when released.


Processor Option 2

The Microchip PIC32MX110F016B.

I went to Microchip’s website and worked through their parametric search tools.  I was looking for a device that could use the SPI interface at at least 10 Mbps and at the lowest cost.  There were no 8 bit parts that could meet the SPI requirement.  There were some 16 bit parts that could meet this requirement, but they were the high end parts.  I had to look into the datasheets to see the maximum SPI baud rate.  Since JTAG does not have 8 bit fixed width registers, I will probably have to play some tricks to use the standard SPI for JTAG operation.

Microchip PIC32MX110F016B

Device advantages

  • Two Fast SPI channels (1 for programming, 1 for data storage)
  • DMA transfers for each SPI channel– Frees software up to do data manipulation tasks
  • 5 V tolerant pins
  • I am familiar with Microchip and their IDE — MPLAB X
  • US $1.73 each in quantities of 100
  • Compatible upgrade path if this chip isn’t enough
  • Low pin count — 28 pins
  • Dip Part for prototyping

Device Disadvantages

  • I am unfamiliar with microchip 32 bit architecture
  • Limitations on free C compiler — mostly in optimization