Electronics design review (Hardware V00D)

The circuit is almost ready to go to layout again. This week I took a close look at the schematic design to look for errors and unfinished tasks.  By the way, you can put notes on a schematic to help you find anything you put off for later.

I have received the PCBs for my client, but I haven’t had the chance to populate the first one yet.  This means I haven’t had a chance to test the charging circuit yet. The availability of inexpensive PCB fabrication like OSH park has made a mini PCB test run reasonably priced.  You can now design a development board that exactly meets your requirements very inexpensively.  Since each iteration of the this design isn’t costing a lot, I am testing multiple changes each time. This allows me to work with devices that I am completely inexperienced at very low risk.

I started with the lithium cell charging circuit. I verified the input from the micro USB connector is tied to the input of the management chip.  I copied the timing and current limit device values from my client’s design.  The lithium cell (connector) is connected to GND and the dedicated pin on the management chip.  The status outputs are tied to LEDs so I have some indication of what is happening during charging. I may try to incorporate these signals later in the design. The system power output is connected to the 3.3V regulator which is working well on the two test boards I have already built.

Next I looked at the SPI RAM Chip select logic.  The transistor Q6 turns on when CS0 is low; this pulls the chip select line for U2 high preventing U2 from contending with the SPI bus when the flash chip is being accessed.  There is a diode blocking the high from pulling GPIO15 high during reset. There is a pull down resistor for when GPIO15 is low and CS0 is high to activate U2 chip select. This is untested but the design looks like it will work.  I chose 22K resistors for the pulldowns on GPIO15 and U2 chip select as a balance between current required when GPIO15 is high and the speed at which U2 chip select will fall when released.  Since I don’t know the amount of capacitance of that circuit, I may have to change that resistor value later.  Good place to put a note on the schematic.

U2 Schematic notes

The level shifter U3 is untested, I should test it before I go to layout. Another note.

I decided earlier that the voltage booster was working but needs to have an isolated ground on the PCB layout.  I have added an inductor between the boost GND and the system GND.  This allows for some experimentation.  I can just bridge the pads with solder, I can put a resistor in there, or I can install the inductor. If isolating the GND is enough, that’s great.  The resistor would help provide better filtering but could cause problems.  The inductor is best filtering but will slow down signal transitions of the high voltage. I also gave the net name GNDpp to the isolated GND.

Vpp GNDpp isolation

The transistor driver for VPP is untested, because I haven’t had the positive voltage available. I could have attached a 12 volt source and tested it but it’s a simple circuit. It should work. The analog switch is working, nothing to review with it.

Finally, the programming control pins RST and GPIO0. I am not happy with the resistor connections. I have decided to copy the design from the NodeMCU dev board.  It is simple and works well on the dev board.  The only thing I am concerned about here is how much current the UART bridge pulls when not connected to USB.

CH340 Crossslink

Use the GitHub link to get a current copy of this design. After testing, I will go to layout.

I would love to hear any questions or suggestions.  If you would do this differently, please comment.

SPI RAM testing (Firmware V00F)

The SPI RAM was still unproven.  I want to test it before I do a new layout.  I checked the SPI lines with a Saleae Logic16 which unfortunately can only sample 3 lines at 100MHz  I was concerned that the SPI RAM would be on the SPI bus at the same time as the FLASH.  This could occur anytime the CS0 and the HSPI CS were low at the same time while the processor was writing or reading from the flash. So I connected to the two chip select lines and the SPI clock line. I triggered capturing off of the first falling edge of CS0.

SPI Enables

I configured GPIO15 to HSPICS at the beginning of user_init and it appeared to not make any difference.  I then changed it to a digital pin and set it high and still didn’t appear to make a difference. So I guessed something I was initializing was causing it to change back to the mode it had been in before.  I set the Pin to a Digital output and set it high at the end of user_init, and it worked.  Since that worked, I tried changing the last step in user_init to set up the SPI overlap configuration. This also works.  It looks like that for about 300 ms there is bus contention between the SPI RAM and the FLASH memories.  This has got to be solved before I go to a new layout.

What I need is to keep the SPI RAM CS line high anytime the FLASH CS is low but follow GPIO15 the rest of the time. It’s helpful to look at in a truth table.

 CS0   | HSPICS |    CS
   0   |    0   |    1
   0   |    1   |    1
   1   |    0   |    0
   1   |    1   |    1

There is only one zero in the table, this means it can be represented as an or gate. If I invert CS0 and or the signals together I would get the results I want. I figured out a circuit that would work that just adds a transistor, a diode, and a couple resistors. A PNP transistor to pull the line up when CS0 is low and a diode to block the current when GPIO15 is driven low at the same time that the RAM CS is pulled high.  There will have to be a pulldown resistor to make sure the CS will go low when it needs to.

I have pushed these minor firmware changes to github.

SPI Overlap


I got the Sigma Delta putting out a waveform that I was looking for. But when I connected the power rail to the input of the inductor for voltage boost, the system stopped booting correctly.

I had several possible problems to look at.

GPIO16 is tied to reset on some ESP8266 modules allowing wake from deep sleep based on the RTC. I tried taking it back out of the code and I am still getting unexpected boot up activity. Doesn’t appear to be the problem, I may have to come back and have another look.

I haven’t built with the change of memory maps until last week. The bootloader may not be linking properly with my code or I may have made some mistakes pertinent to the linker. I removed the new files and recompiled without GPIO16 support and therefore a smaller memory map that fits without modification of the link files. I commented out most of the code and it still would not boot into my code. Code doesn’t appear to be the problem.

Finally, the boost circuit may draw very large amounts of current that will cause noise back into the rest of the system.  Power may not be stable enough for reliable operation. I disconnected the 5V from the boost circuit and got reliable boot.  I need the boost circuit to work, so I replaced the 10 ohm resistor with a 68 ohm resistor( Maximum current draw from USB would be 5v/68Ohms or 74mA). It wasn’t enough. So I tried 220 Ohms, then I tried 1KOhms.  This means the maximum current I can provide to VPP is significantly reduced.  I will add capacitance to the PCB on the 5V lines to allow for better noise immunity. The board is booting reliably.  The problems I had earlier with the CH340G were probably related to this problem as well.  I still needed to run the CH340G at 3.3V, So I am glad I changed that already.

The boost circuit is not able to create a voltage above 5v with the 1K resistor. Testing the ADC reading, I discovered I had R8 and R9 Cross labelled on the board. So I switched the labels on the layout.

The firmware is running again.  I can put a pulse stream out to the Voltage Boost circuit but the 1K limiting resistor is too large to work correctly.


Functional testing for layout V00B

For testing purposes, I chose to put the code that I can control over a serial terminal into the ESP-12E. I had to make a few modifications for the new design.  The version for the last design/layout is archived on GitHub, I can easily go back to it if I find a need.

On the new design, several pins are different than before.  I changed the sigma delta output from GPIO2 to GPIO4 so it can drive the voltage boost circuit. I set GPIO16 to output low to turn on the voltage boost circuit, and I set GPIO2 to output low so that the boosted voltage would be on the programming header.

I had to make adjustments to the build environment to build esp-ginx.  Apparently I managed to break the build environment for the SDK in the process.  For esp-ginx I had updated to the newest version of the compiler toolchain.  This removed some symbolic links, so I couldn’t compile at all.  I fixed the symbolic links, and I am able to compile now, however it compiles without any errors but doesn’t make a binary file. Turns out I was in the wrong folder to link properly. Next the calls to GPIO16 causing a failure to compile. I needed to bring in the files gpio16.h and gpio16.c into the project.  Then the project failed to link with the errors “undefined reference to `gpio16_output_conf'” and “undefined reference to `gpio16_output_set'”.  This turned out to be where I placed the file gpio16.c, once I put it in the user folder, that error went away. Then I got a new Error “`.irom0.text’ will not fit in region `irom0_0_seg'” which means I ran out of code space.

While I was looking at the makefiles I noticed a section for configuring the memory in the sdk base folder. SPI SIZE MAP = 4 or 6  both match the ESP-12E. Setting it to 4 and then 6 didn’t fix the problem. Setting BOOT = new and APP to 1 got it to compile and link without errors.

I installed the new code and I get the menu up on my terminal window.

The sigma Delta doesn’t seem to be outputting anything on any pin. This means more testing.



Merry Christmas!

The PCBs came in today, they look great.  Of course I will need to make the modifications I mentioned last week.  I haven’t received the CH340G chips yet. I will wait until I receive them before I start building.


This week, I wanted to add  a slider to set the Sigma Delta output that drives the voltage booster to the web interface.  I didn’t know javascript at all so, I went to an online tutorial at Codecademy.com. This tutorial is very basic and even explains the basic concepts of programming in general.  I didn’t learn enough to set up a slider, I did learn enough to do some testing.

I quickly got the Sigma Delta output working in GPIO12 by copying the necessary code from the test project I was using. I then added a call to config_sigma_delta() from user_init() in user_main.c.  I also added a call to set_sigma_delta_duty() from my test code in cgi_relay.c.  Of course I added includes to sigma_delta.h in both of those files.  I then changed the Sigma Delta output from GPIO12 to GPIO4 to match the HV_pulse line used to run the switched coil.

Now if I hit the say Hello button, It changes the Sigma Delta output duty cycle. also, the Chart on the index.html page gives the current reading from the ADC once every 5 seconds.



First web page

I have the web server up and running which is great.

While reviewing my design, I found a few mistakes in the layout.  These mistakes are easily fixed with either a jumper wire or solder bridge, so I can keep on testing when the new PCBs arrive.

The web server isn’t working as easily as I had hoped.  I made a copy of the cats web page in the project, added my banner photo from this site and added html links in each page to point to the new page. With my picture added, It wouldn’t compile.  I am sure there is enough room in ROM, so I just need to figure out some settings. I removed the picture from the project and it compiles. I added an entry in my hosts file to point to smart.relay.com. When I go to smart.relay.com on my network it seems to work most of the time.  Speed and reliability will need to be worked on.

My new page unfortunately comes up blank. If I add .html to the end of the url my page loads correctly.  I went through the pages and added the .html ending to each link.  I don’t understand why this is happening this way.

I opened and modified the eagle.app.v6.ld  I changed the irom_0_seg  line. I changed the len value from 0x51000 to 0x80000.  This allowed me to add the banner photo into the project.  I don’t know if this can cause problems.  Assuming the value was at 0x51000 for a reason gives me reason to be concerned about it.  It’s possible that I have allowed data to overlap which could cause major problems. I need to learn how the .ld linker files work.


Web Server firmware

I am waiting on the stuff I ordered last week.  The CH340G chips are probably going to take the longest at 3 to 4 weeks.

To start with I updated my virtual machine to keep it current, I downloaded V1.5.0 of the Espressif SDK, and updated the lubuntu inside of the virtual machine.

I spent this week trying to get the chip running as a web server.  On the ESP8266 forum I found about a project called esp-ginx.  It is a web server with a lot of features.  For me it looks like a lot more than I need.  This is good for this design, I can cut away or ignore the features that I won’t be using or needed.

I downloaded the zip from github.  I ran make from the wrong directory and it failed to compile.  Finally realizing I need to run make from the project directory I was able to get it to compile without any errors.  I then uploaded it to my board and it didn’t work.  I was continuously getting fatal exception (0) on the serial port at 74800 baud.  Thinking that my RAM chip might be causing problems, I decided to remove it and try again.  Still no success.

I then tried to load the code into the NodeMCU board that I also use for testing. I got the same results with it.  I re-loaded my code into my board and got it back to working.  After many tries I finally realized tried putting the app folder in my home directory without any of the SDK files and it compiled.  I loaded this to my board with the commands: make clean, make html, make, and make flash.  The virtual machine had crashed and I needed to reboot my whole system before this worked for me.

This has been very frustrating just to find out that I didn’t understand the way to set up my files.  After I got the web server up and running, I added an entry to my hosts file on my computer.  I made an entry that pointed to he ip address of the board and associated it with smart.relay.com.


Design Review V00B

Design reviews should be done often, at least just before a new design goes to fabrication.

During testing I had wished for some test pins at the edge of the PCB for verification. I want to add and label test pins for Reset, Txd, Rxd, 3.3V, SCK, MOSI, MISO, IO2, IO3 and L1 pulse.

I added these testpoints to the schematic along with a ground that’s easy to get to. I am putting them into a through hole 1×12 connector. I moved P1 test into the same header. In layout, I’ll place this connector next to the edge where I can get a clip lead connected for testing.

USB to Uart chip completely changed, copied reference design from NodeMCU design. It’s helpful to look at a second design for a sanity check. Everything matches up to an Arduino clone schematic found on the web.  I had left DCD, RI, DSR, and CTS unconnected.  Leaving inputs unconnected can cause problems.  These connections may have internal pullups/pulldowns but I couldn’t find any reference to that in the datasheet. Each of these lines indicates data is ready to flow when held low, I put pulldowns on each of them.

I had changed the SPI connections to correct the mistakes I had made earlier, I have gone back to verify these connections and found conflicting information. I traced the gerber image I had found to get the pinout I currently have. If it’s not correct, I will have the test pins to help me figure out the  correct pinout.

I had replace the port expander with a shift register still using the SPI to fill the register. According to the datasheet, the data shifted in will be latched on the rising edge of the RCLK pin.  If I treat RCLK as a Chip Select Pin on the SPI, a one byte write will set all of the outputs very quickly. This appears that it will work well.

The VPP circuit changes are a big gamble. I don’t know if it will work.  I am adding a 0.1 µF capacitor to the output to reduce output noise.  I am adding a 10 Ohm resistor and a 100 µF capacitor to filter noise from getting back into the rest of the system. I need to isolate the ground of the high voltage circuit to only connect to regular GND Net at only 1 place on the layout. This will help reduce noise transfer back into the rest of the system. The design update is on GitHub, use the link in the upper right hand of the page.


Updating Schematic V00B

In the last few posts, I found several problems with the design as well as found some ways to reduce Bill of Material costs.  I also want to make soldering of the parts easier for a hobbyist.

I had problems using the CH340G chip on my NodeMCU board.  I couldn’t find any references to this problem on the internet.  So I replaced U8 (the CP2104 USB to UART bridge) with the CH340G USB to UART bridge.  I inverted DTR and RTS  and connected them to GPIO0 and RST respectively.  Using transistors as the inverters means that when U8 is not powered, it won’t draw those two lines down.  This is looking forward to when the design is battery powered.

I used the NodeMCU schematic as reference during this part of the design since it is close to what I want to do with this part of the design.

I changed the reset push-button switch to pads on the board and left the upload push-button switch unchanged but don’t plan on installing it unless I run into problems programming the board.

I also want to make things smaller, U9 is a large part of the board.  A shift register can do the same thing and be less expensive. I found the 74HC595 to replace U9. I am still clocking data in using the SPI bus, and then latching it with a pulse from GPIO5.

For the High voltage, I removed the AAT1230 and replaced it with two logic level FETs. One to disable the circuit to drop current draw when in low power mode connected to GPIO14. The other the pulse stream that generates the current through the inductor connected to GPIO4.  This means all the pins on the module are used up again.

Kicad schematic and layout can now be found here. The pcb layout is not current to the schematic, I still need to do a design review before I start the layout.


ADC and PWM V00D

I have implemented the Reading the ADC from a keystroke (R) sent over serial. I have implemented the PWM on GPIO12.  My initial testing of the PWM has a lot of jitter and didn’t perform at the frequency I configured.  I want to set up a Hardware PWM and see how it performs.  Jitter and frequency can be important when running a switching power supply, so I want to get this right. I set GPIO2 high to select Target voltage as the input to the ADC and set a variable power supply at 0.3 volts tested it and got results around 300, then set it to 0.5 volts and got ADC results around 500 indicating it’s working as expected.

The chip doesn’t have a PWM instead it has a built in sigma-delta pulse generator.  It creates a stream of pulses to achieve the specified duty cycle by adding more pulses to fill in the middle. The chip will connect the sigma delta generator to any GPIO pin I choose.  I can use any free pin to drive the boost inductor switch. If I optimize the inductor for the width of the pulse, I should get very efficient voltage conversion.

There is no API configured for the Sigma Delta unit.  I had to write directly to the registers that set the pin connection and the Sigma Delta unit.  I had to do a lot of experimentation to understand how to set up the Sigma Delta pulse generator.  There is a piece of example code on Espressif’s forum that doesn’t work correctly, but gave me the information I needed to figure out how to configure the unit.  The example code tries to be very generic, and my code is over-simplified for testing.