Target interface analysis

Website security:

I have updated this website to default to TLS for connections.  I have a certificate supplied by my hosting provider.  I have also turned on member accounts.  I am hoping this will make it more convenient you, the readers to join the conversation.

Voltage level shifter:

I am still trying to decide the best way to go for adjusting to the target platform voltage.  SPI typically needs 3 bits output (SS, SCLK, MOSI) and one bit input(MISO)  Sometimes SPI needs more. JTAG needs 4 pins output(TCK, TMS, TDO, TRST) and one bit input(TDI). I found the JTAG signal description on this page. I2C needs two bits of bi-directional open drain signals.  I don’t know of any MicroControllers that can be programmed over I2C but there are flash memories that are programmed that way.

Based on this information, I can see that I would want 4 bits of output and 2 input along with a 2 bit open drain bi-directional.  This gives me a total of eight bits of data available to connect to the target device.  In addition to that, I need Target Vcc and GND and Vpp.

I think that I will multiplex the I2C lines so that they can also be regular inputs or outputs.  If I use multiple 2 bit level shifters,  I will need a shift register to control the 3 State and direction pins.

Updating the schematic:

While looking at the signals I wanted to expose to the target, I noticed some changes I wanted to make to the schematic.  I connected GPIO0 to the A_SEL/Vpp(gnd) line.  This freed up GPIO5 for I2C. I moved the Vpp drive control line from GPIO2 to GPIO16 and then moved HVPulse to GPIO2. This freed up GPIO4 for I2C.  I deleted the level shifter to make it easier to think about the design.

To see how things looked, I added the 2 bit level shifters(74LVC2T45) and a I2C lever shifter(PCA9306). I then added a Serial shift register connected to the HSPI and used the TXD and H_CS together as the latch line.

I made a lot of changes this week. I am going to let these changes sit a bit before I go to layout.  I’m not sure I like the current state of the design. Also, I still want to test one more change to the Vpp generation circuit. I have uploaded the design in it’s current state to Github, I don’t have much confidence it will stay unchanged.


It’s been a month since I last posted.  If your regularly following this blog, I am sorry.  I am trying to get back into the routine of posting every week.  I am not very motivated and that makes it tough.  I am still looking to hear from you.  Please let me know if this has been useful to you.

Leave a Reply

Your email address will not be published. Required fields are marked *